Polishing processes are used in the manufacturing of microelectronic devices to form flat surfaces on semiconductor wafers, field emission displays, and other microelectronic substrates. For example, the manufacture of semiconductor devices generally involves the formation of various process layers, selective removal or patterning of portions of those layers, and deposition of yet additional process layers above the surface of a semiconducting substrate to form a semiconductor wafer. The process layers can include, by way of example, insulation layers, gate oxide layers, conductive layers, and layers of metal or glass, etc. It is generally desirable in certain steps of the wafer process that the uppermost surface of the process layers be planar, i.e., flat, for the deposition of subsequent layers. Polishing processes such as chemical-mechanical polishing (“CMP”) are used to planarize process layers wherein a deposited material, such as a conductive or insulating material, is polished to planarize the wafer for subsequent process steps.
Due to its desirable electrical properties, copper is being increasingly utilized in integrated circuit fabrication. However, the use of copper presents its own special fabrication problems. For example, the controlled dry etching of copper for ultra large-scale integration (ULSI) applications is very costly and technically challenging, and new processes and techniques, such as damascene or dual damascene processes, are being used to form copper substrate features. In damascene processes, a feature is defined in a dielectric material and subsequently filled with the conductive material (e.g., copper).
In order to ensure that the different features of relatively small integrated circuits (e.g., less than 0.25 micron or less than 0.1 micron) are sufficiently insulated or isolated from one another (e.g., to eliminate coupling or “crosstalk” between features), dielectric materials with low dielectric constants (e.g., less than about 3) are being used in the manufacture of damascene structures. However, low k dielectric materials, such as carbon doped silicon oxides, may deform or fracture under conventional polishing pressures (e.g., about 40 kPa), called “downforce,” which deformation or fracturing can detrimentally affect the substrate polish quality and device formation and/or function. For example, relative rotational movement between the substrate and a polishing pad under a typical CMP downforce can induce a shear force along the substrate surface and deform the low k material to form topographical defects, which can detrimentally affect subsequent polishing:
One solution for polishing conductive materials (e.g., copper) in low dielectric materials with reduced or minimal defects formed thereon is to polish the conductive material using electrochemical-mechanical polishing (ECMP) techniques. ECMP techniques remove conductive material from a substrate surface by electrochemical dissolution while concurrently polishing the substrate with reduced mechanical abrasion compared to conventional CMP processes. The electrochemical dissolution is performed by applying an electric potential or bias between a cathode and substrate surface to remove conductive materials from a substrate surface into a surrounding electrolyte or electrochemical-mechanical polishing composition.
While several suggested formulations for electrochemical-mechanical polishing compositions can be found within the art, few, if any, of these electrochemical-mechanical polishing compositions exhibit desirable polishing characteristics. For example, the suggested electrolytes or electrochemical-mechanical polishing compositions may exhibit polishing rates comparable with conventional CMP processes without the need for the application of an excessive downforce, but the electrolytes or electrochemical-mechanical polishing compositions can cause excessive dishing of the conductive material which can lead to erosion of the dielectric material. The topographical defects resulting from such dishing and erosion can further lead to non-uniform removal of additional materials from the substrate surface, such as barrier layer materials disposed beneath the conductive material and/or dielectric material, and produce a substrate surface having a less than desirable quality which can negatively impact the performance of the integrated circuit.
Accordingly, there remains a need for an electrochemical-mechanical polishing method that exhibits relatively high removal rates of substrate material at low downforce while minimizing dishing and erosion of the substrate. The invention provides such an electrochemical-mechanical polishing method. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.